Toshiba’s new device structures aim to boost efficiency and reliability in high-temperature power conversion systems.

Example of 3rd generation SiC MOSFET. Image used courtesy of Toshiba

Toshiba’s Advancements

Toshiba’s research focused on improving trench MOSFET and Schottky barrier diode SiC devices by redesigning their internal structures to minimize on-resistance and improve high-temperature stability.

Trench MOSFET structure with bottom P-well. Image used courtesy of Toshiba

For SiC trench MOSFETs, Toshiba introduced a protective structure known as a Bottom P-well within the trench. This modification was intentionally engineered to manage the electric field impacting the gate oxide. By optimizing the grounding resistance of the Bottom p-well, Toshiba established a direct correlation between this parameter and unclamped inductive switching ruggedness, which evaluates a device’s resilience to inductive switching stress. The testing revealed that the new trench structure achieved approximately 20% lower on-resistance compared to traditional planar SiC MOSFETs, while also enhancing UIS performance.

The structure of a conventional (a) and super junction (b) SiC SBD. Image used courtesy of Toshiba

In parallel, Toshiba developed a 650 V-class semi-super-junction SBD featuring vertically arranged p-type and n-type pillars in the drift region. This design flattens the internal electric field distribution to reduce resistance escalation at elevated temperatures. Experimental comparisons showed a 35% reduction in on-resistance at 175°C when contrasted with conventional SiC SBDs. This substantial improvement positions the SJ-SBD as a more stable component for systems operating under extreme thermal loads.

Understanding UIS Ruggedness

In power electronics, the ability to withstand inductive switching events without failure is synonymous with device reliability. In many cases, this capability can be quantified by unclamped inductiveswitching ruggedness. This performance metric measures how well a power device tolerates energy surges caused by inductive loads during switching.

When a power device turns off while driving an inductive load, the collapsing magnetic field generates a voltage spike that can significantly exceed the device’s rated limits. Without adequate design provisions, this spike may damage the gateoxide, overheat internal structures, or trigger avalanche breakdown. Traditional design strategies often involve trade-offs between UIS ruggedness and conduction efficiency.

Example of UIS waveforms. Image used courtesy of Gonzalez et al.

Improvements in UIS performance are often related to the electric field protection architecture and how the device dissipates energy and controls voltage gradients across sensitive regions. Toshiba’s introduction of a Bottom p-well structure in the trench region addresses this by altering the grounding resistance that governs electric field distribution. Reducing this resistance limits the field intensity at the gate oxide and enhances the device’s ability to survive high-energy switching events without failure.

Accurately modeling and controlling this parameter allows engineers to tune the UIS threshold without compromising other electrical characteristics.

Toshiba’s Outlook

By lowering on-resistance and improving ruggedness without compromising thermal stability, Toshiba’s new technologies aim to support the industry’s current trajectory toward more compact and efficient systems. According to Toshiba, the company plans to further refine these technologies and move toward commercialization, but has not announced a specific production timeline.